// Собрать можно так
// $ verilator --binary test.sv && ./obj_dir/Vtest
// Добавить --timing --trace
// $ verilator --timing --trace --binary --main sim_test.sv

/* verilator lint_off DECLFILENAME */
/* verilator lint_off UNUSEDSIGNAL */
/* verilator lint_off BLKSEQ */
/* verilator lint_off UNDRIVEN */
`timescale 1ns/1ps
module dut(input logic clk, input logic a, input logic b);
   logic c;
   reg [3:0] cnt=0;
   
  always_ff @(posedge clk)begin
     c <= b;
     if(cnt<10) cnt <= cnt + 1;
     else       cnt <= 0;
     
     $display(" num %d t=%t", cnt, $time);
  end

    a1: assert #0 (!(a & c)) $display("a1:Pass: a=%d c=%d b=%d",a,c,b); 
       else $display("a1:Fail: a=%d c=%d b=%d",a,c,b);
    a2: assert final (!(a & c)) $display("a2:Pass: a=%d c=%d b=%d",a,c,b); 
       else $display("a2:Fail: a=%d c=%d b=%d",a,c,b);

endmodule
program tb(input logic clk, output logic a, output logic b);
  default clocking m @(posedge clk);
  default input #0;
  default output #0;
  output a;
  output b;
  endclocking
  initial begin
      $dumpfile("out.vcd");
      $dumpvars();

//     a = logic'($random());
//     b = logic'($random());
repeat(4) begin
    a = 1;
    b = 0;
    ##10;
//     b = ~b;
    b = 1;
    ##1;
//     a = ~a;
    a = 0;

   end
           $finish();
  end
endprogram


module sim_test;
   bit clk;
   logic a, b;
   
   always #5 clk <= ~clk;
   dut dut(.*);
   tb tb(.*);
   
//   initial begin

//      byte a;
//      byte b;
//      $dumpfile("out.vcd");
//      $dumpvars();

//      repeat(8) begin
//	 @(posedge clk);
//	 a = logic'($random());
//	 b = logic'($random());
//	 $display("a=%0h b=%0h time %0t", a, b, $time);
//      end
//      $finish();
//   end // initial begin
         
endmodule
